The overall class diagram for the SoC with JTAG debug support
incorporating a UART, terminal and simple debug logger is shown in
Figure 11.3. The design is similar
to that for the SoC with interrupts (see Section 10.1.1). The overall diagram is now quite
complex, so, for clarity, only those classes new to the JTAG
enabled design are shown. The remaining detail was shown earlier in
Figure 10.2.
The Or1ksim ISS wrapper is subclassed to add the new target port
and handler for JTAG. This needs a SystemC
mutex in order to ensure that access to the
JTAG port does not clash with running of the underlying Or1ksim
model. This is discussed in more detail in Section 11.2.
The new logger class, JtagLoggerSC provides a
simple stream of debug JTAG register transfers through the debug
TLM 2.0 interface. That interface makes use of the mandatory
extension class JtagExtensionSC to specify
details of the JTAG register being shifted.
