11.3.1. Adding JTAG Interface Functions to the Or1ksim library

These additional functions allow the external SystemC model to call into the Or1ksim ISS to request debugging activity through use of a JTAG register. The ISS requires that interrupts are not taken mid-instruction (for example while a peripheral memory access upcall is in progress). However it is up to the caller to enforce this restriction.

JTAG registers are represented as a byte vector, with the least significant bits in the lowest numbered byte. Where the number of bits is not a multiple of eight, it is the most significant byte which holds the odd number of bits, shifted to the least significant position within the byte. Thus for a 12-bit register, bits 0-7 would be in byte 0 and bits 8-11 would be in the least significant 4 bits of byte 1.

```
double  or1ksim_jtag_reset ();
		
```
or1ksim_jtag_reset requests the Or1ksim ISS debug unit go through a JTAG reset cycle to put the Test Access Port (TAP) in a consistent state. It returns the time taken in seconds.
```
double  or1ksim_jtag_shift_ir (unsigned char *jreg,
			       int            num_bits);
		
```
or1ksim_jtag_shift_ir shifts the JTAG register specified by its arguments through the JTAG instruction register. It returns the time taken in seconds.
```
double  or1ksim_jtag_shift_dr (unsigned char *jreg,
			       int            num_bits);
		
```
or1ksim_jtag_shift_dr shifts the JTAG register specified by its arguments through the JTAG data register. It returns the time taken in seconds.

The behavior of the debug unit in response to JTAG register transfers is fully documented in descriptions of the Test Access Port [3] and the OpenCores Debug Unit [2].

These functions are a standard part of the Or1ksim 0.4.0 library.

	Caution
	These functions are not a standard part of the Or1ksim 0.3.0 library.