Before building the Verilator model it is necessary to consider the test bench, which will replace orpsoc.v and or1200_monitor.v. This chapter looks at the overall structure of the test bench, and the detailed implementation of the pure SystemC components.

There are also a number of components which tie in closely with the actual Verilator model (for example to access signals in the model, or to generate VCD traces from the underlying model). These are covered in the chapter on building the Verilator model (Chapter 6).

The structure of the SystemC test bench is not that different to the Verilog test bench used with event driven simulation (see Chapter 4). The DUT is provided by the Verilator model (class Vorpsoc_fpga_top) and the monitor for l.nop is hand-written as a SystemC class, Or1200MonitorSC.

Two further SystemC classes are needed, one to generate a reset signal (ResetSC) and a second to provide VCD trace functionality of the underlying Verilator model (TraceSC).

The top level of the test bench (the equivalent of orpsoc_bench) is provided by the sc_main function.