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Chapter 7.  Optimizing the Verilator Model

7.1. A Note on Statistics
7.2. Verilator Warnings
7.2.1. The CASEX Warning
7.2.2. The VARHIDDEN Warning
7.2.3. The IMPLICIT Warning
7.2.4. The WIDTH Warning
7.2.5. The CASEINCOMPLETE Warning
7.2.6. The COMBDLY Warning
7.2.7. The UNOPTFLAT Warning
7.2.8. Fixing Language Conflicts
7.2.9. Summary of Performance Gains from Verilator Warnings
7.3. C++ Compiler Optimizations
7.3.1. Use of OPT_FAST, OPT_SLOW and OPT
7.3.2. Choice of optimization level
7.3.3. Compiler Profiling
7.4. Profiling the Completed Model
7.5. Summary of Performance Gains Through Optimization

The Verilator model in the previous chapter was generated at the expense of turning off most of the warnings and restricting the language to IEEE 1364-2001 Verilog.

For much existing RTL, this is a satisfactory endpoint. However fixing the various warnings can allow Verilator to generate better quality code. This chapter takes each of those warnings in turn and shows how to handle them.

There is a general approach, which applies to most warnings in Verilator An individual warning can be disabled by surrounding the troublesome code by a verilator lint_off  and verilator lint_on  comments specific to the warning. For example to disable a CASEX warning use the following:

      // verilator lint_off CASEX

      <troublesome code>

      // verilator lint_on CASEX
    
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