The Or1ksim ISS described in Chapter 4 and the UART described in described in Chapter 6 can be put together as a minimal SoC. However a test bench is needed to exercise that SoC

The usual way of exercising a SoC with a UART is to connect a terminal to the UART. This section describes a suitable SystemC model of a terminal and how to connect it to create the complete SoC.

This is not a TLM 2.0 component—the interfaces are standard SystemC buffers, so the description is less detailed. However it serves to illustrate an important general technique when using SystemC—how to interact with the operating system functions.

The problem is that many operating system calls block. Consider modeling the terminal as a thread which reads characters from a console window. This will block until characters are typed. However the block does not use the SystemC wait call, so SystemC is not aware that the thread has yielded. The simulation will hang until characters are received.

This implementation of the terminal will show how to wrap non-blocking versions of operating system functions with SystemC events, to give versions that block correctly using SystemC wait, so allowing the thread to yield.

The code for the terminal module (TermSC.cpp and TermSC.h) and the main program (simpleSocMainSC.cpp may be found with the UART module and extended Or1ksim ISS wrapper code in the sysc-models/simple-soc directory of the distribution.