The example, a simple SoC, is based on the Or1ksim ISS for the OpenRISC 1000 architecture. The OpenRISC 1000 architecture is a conventional 32-bit DSP/RISC design, with optional caches and MMU. Or1ksim is an interpreting ISS written in C, which in its standard configuration models main memory and a number of peripherals as well as the CPU itself.

A key feature of Or1ksim is that it is single threaded and the code is generally not re-entrant. Much of the challenge in wrapping such an ISS is ensuring consistency within a multi-threaded SystemC environment.

Information on obtaining and setting up the open source Or1ksim simulator and its tool chain are given in Embecosm Application Note 2. The OpenCores OpenRISC 1000 Simulator and Tool Chain: Installation Guide. [4].

For Chapter 4 through Chapter 9 the Or1ksim ISS is configured to model only the CPU and main memory, with example peripherals modeled as separate SystemC modules. For Chapter 10, the ISS is configured to model the data and instruction MMUs and a programmable interrupt controller (PIC). This allows the ISS to support interrupt driven peripherals and hence Linux

In Chapter 11 a second thread is introduced to the wrapper to model the JTAG debugging interface. This allows the model to be run under the control of a debugger such as GDB