Services and Modeling for Embedded Software Development
Embecosm divider strip
Prev  Next

Chapter 3.  Case Study: A Loosely Timed SoC Using TLM 2.0

3.1. The Example Designs
3.1.1. Or1ksim ISS TLM 2.0 Wrapper with Logger
3.1.2. Simple SoC Design
3.1.3. SoC with Interrupt Support
3.1.4. SoC with Debugger Support
3.2. Example Code
3.2.1. Source Code for Example Models and Programs
3.2.2. Code Documentation
3.2.3. SystemC Model Coding Conventions
3.2.4. Derived classes
3.2.5. Configuration

In this case study, TLM 2.0 convenience sockets are used to wrap an existing ISS. This is then built into a simple SoC using additional hand-written TLM 2.0 components.

Modeling uses the TLM 2.0 generic payload with no extensions. It is independent of the specific bus architecture that will be used in the implementation.

The ISS used is from the OpenCores (www.opencores.org) project. This open source project has developed a complete 32/64-bit architecture, the OpenRISC 1000, complete with GNU compiler chain, architectural simulator and Linux port. This application note uses the OpenRISC 1000 architectural simulator, Or1ksim as the ISS for all the examples.

The model is constructed in a number of stages:

  1. The basic wrapper for the Or1ksim ISS is built using TLM 2.0 convenience sockets and tested with a simple logger. In this first stage timing is ignored—this is effectively an untimed model. See Chapter 4 and Chapter 5.

  2. A model UART is added as an example peripheral, demonstrating how TLM 2.0 and existing SystemC technologies can be mixed. See Chapter 6.

  3. A model of a terminal is added as a test bench for the SoC. This demonstrates how to add SystemC components which use operating system I/O without blocking the SystemC thread. See Chapter 7.

  4. Synchronous timing is added to each component, making the model loosely timed. See Chapter 8.

  5. Temporal decoupling is added to the Or1ksim ISS, UART and terminal, to improve the performance of the model. See Chapter 9.

  6. Interrupt modeling is added to the UART and the Or1ksim ISS, allowing the model to run Linux. See Chapter 10.

  7. A second thread, modeling the JTAG interface to the processor is added to the wrapper. This demonstrates how the ISS wrapper can be multi-threaded, while the underlying OpenRISC 1000 ISS remains single threaded. This interface allows the model to be driven from a debugger such as GDB. See Chapter 11.

Simple applications, compiled with the OpenRISC 1000 tool chain are used throughout to exercise the model components. The final model is demonstrated booting a Linux 2.6 kernel.

Embecosm divider strip
Prev   Next
2.3.5.  TLM 2.0 Convenience Sockets  Home 3.1.  The Example Designs

Copyright © 2008, 2010 Embecosm Limited