Embecosm brings together the very best engineers and our unique technology. Embecosm services, tools and models boost productivity, reduce costs and are the key to successful firmware development.

• Integrated SoC firmware development using high level models, simulation, FPGA and final silicon.
• Seamless, unified SoC debugging from initial model to final silicon.
• Standards based hardware modeling, including OSCI SystemC TLM 2.0 compliance.
• Support, consultancy, tutorials and training throughout the product life cycle.

Technology Leadership

Embecosm's debug technology for embedded development gives you access to the complete system-on-chip. Not just the processor core, but peripherals, whether modeled or in silicon, are accessible throughout the design life cycle.

Our engineering services offer world-class skills and expertise in embedded tool chains and system modeling.

Standards Based and Open Source

Embecosm is standards based and open source. Our tools, implementation code, user guides and application notes are freely available for download.

With Embecosm open source technology, tools and models, all the risks of supplier "lock-in" are eliminated. Embecosm's support is there to help you gain maximum benefit from the technology.

NEWS

June 2009. The new Embecosm Proxy GDB RSP Server is now available for download. This is an essential tool for any developer porting GDB to a new embedded target. Full details on its download page.

May 2009. Open Source for Hardware by Embecosm CEO Jeremy Bennett, published this month in "The Ring", is available for download on the new articles page.

April 2009. Embecosm has moved to new, larger offices in Lymington, UK. Our new address and telephone number are available on our contact page.

March 2009. Embecosm publishes a new application note demonstrating how to connect the GNU Debugger to cycle accurate SystemC processor models using the Remote Serial Protocol (RSP).

This is core technology for any engineer developing firmware using cycle accurate models. Full source code of all examples is included. The application note and examples are now freely available on the application notes page.

February 2009. Updated examples for SystemC TLM 2.0 modeling are now available on the software packages page. These models are for use with the latest version of the OpenRISC Architectural Simulator.

February 2009. High Performance SoC Modeling with Verilator, a new tutorial on SystemC cycle accurate modeling, is now available from Embecosm. In this tutorial, we show by example how to generate a 130kHz cycle accurate model of a 32-bit SoC from its Verilog RTL. This is essential reading for anyone needing more performance from their cycle accurate modeling.

Download the application note from the application notes page and example code from the software packages page or contact Embecosm for your own in-house seminar.

January 2009. Embecosm publishes its SystemC JTAG interface specification, with reference implementation. This is the first in a series of interfaces to simplify debugging complex chips, whether modelled in software or emulated in hardware. Download the application note and reference implemenation free from the download page.