This application note is aimed at engineers needing to interface SystemC to cycle accurate models of devices implementing the IEEE 1149.1 JTAG interface.
Cycle accurate models of devices in SystemC may be written by hand. More commonly they are generated automatically by tools such as Verilator, ARC VTOC and Carbon Design Systems ModelStudio. They may also be implemented using SystemC interfaces to traditional event driven simulation.
Directly interfacing to the JTAG cycle accurate ports of a SystemC model is a complex task, requiring careful modeling of the JTAG Test Access Port (TAP) state machine.
This application note specifies a more abstract interface, allowing the user to simply read and write hardware registers through JTAG. The interface takes responsibility for ensuring the correct sequence of signals is sent through the TAP to achieve the desired action.
The application note and its associated reference implementation provide a practical tool for engineers involved in the detailed design, verification and modeling of complex FPGAs and ASICs.