Transaction Level and Cycle Accurate Modeling
Modern System-on-Chip (SoC) architectural exploration often uses Transactional Level Modeling (TLM), either untimed or using approximate timing. While the system architect will write models of all the custom components, there is the challenge of integrating standard components, for which no SystemC model exists. This can particularly be a problem for processors, where only an instruction set simulator exists. Embecosm has the expertise to wrap existing models with IEEE 1666 SystemC TLM interfaces, allowing them to be used within SystemC architectural exploration.
Once the chip is complete, we have particular experience in cycle accurate modeling of Verilog designs using the open source Verilator tool, creating high performance models of the actual implementation for use in software development, including tool chain development. Where a design is in VHDL we can use the GHDL tool in a similar way.
Instruction Set Simulators
Creating an instruction set simulator (ISS) for a new processor by hand is an extremely time consuming process. The work is intricate, repetitive and very prone to errors, requiring very large numbers of compliance tests.
Embecosm uses GNU CGEN and LLVM TableGen to automate the creation of fast table-driven simulators. From a formal description of the processor architecture and its semantics these tools generate the code for a simulator, assembler/disassembler and even a compliance test framework. A full simulator with its simulator can be created in a matter of weeks.
Embecosm is a pioneer in multi-target debugger integration. Our debugger server is an open source implementation, allowing the user to switch easily between debugging with a high level model or ISS, a cycle accurate model or real hardware. Software and firmware engineers can start to develop code long before actual silicon is available, giving a time-to-market advantage, and also providing pre-tapeout feedback to the processor designers. Whichever target is used, the functional experience is identical (although performance will vary of course).
We provide implementations of the debugger server which support a range of multicore semantic models within the standard GNU Debugger (GDB). This technology is also readily transferable to the new LLVM Debugger (LLDB).
A new feature under development by Embecosm is lockstep debugging for GDB. With this technology, two different models are run in parallel and cross-checked after each instruction. Where a difference is found, an exception is triggered within the code. A silicon chip implementation can be tested using lockstep debugging with a high level architectural model and a cycle accurate model generated from the Verilog or VHDL of the implementation. Real applications run under the debugger will trigger exceptions if there is any divergence in behavior. If required the cycle accurate model can generate a signal trace during debugging, allowing the silicon designer to see exactly why the divergence occurred.
Pre-Silicon Tool Chain Development and Testing
The original reason Embecosm developed so much modeling expertise was to allow us to develop high quality compiler tool chains well ahead of silicon tapeout. Tool chains can be fully tested against a high level architectural model or ISS, then that testing can be repeated against a cycle accurate model of the implementation to check for consistency, and finally tested against the actual silicon.
The comparison between test results with the high level model and with the cycle accurate implementation model is a valuable addition to pre-silicon verification of the design. Any discrepancies between the the two is a possible fault in the silicon design. The case study below shows how this approach improved the quality of the OpenRISC 1000 processor used by NASA in TechEdSat.