Embecosm Application Notes give tutorial case studies on key software technology.

These are made freely available under a Creative Commons Attribution License. Which means that you are free to copy, distribute, make derivative works and commercial use of them. All we ask is that you give credit. For further information see the license details.

They can be read online or downloaded as a PDF or HTML archive. The DocBook XML source can be found on GitHub.

  • EAN 1. Building a Loosely Timed SoC Model with OSCI TLM 2.0: A Case Study Using an Open Source ISS and Linux 2.6 Kernel (Issue 2, May 2010).

    This application note describes by example how to build a simple SoC, capable of running a modern Linux kernel, using OSCI TLM 2.0 convenience sockets.

    Issue 2 has been updated to use the latest patch release, 2.0.1 of the OSCI TLM environment. It adds a new chapter on transactional modeling of the IEEE 1149.1 JTAG debug interface.



  • EAN 2. The OpenCores OpenRISC 1000 Simulator and Tool Chain: Installation Guide (Issue 3, November 2008).

    This application note describes how to install the OpenRISC 1000 architectural simulator, associated tool chain and Linux 2.6 kernel. This open source architecture, simulator and tool set is used as a case study in Embecosm application notes.

    The tool versions covered are GNU binutils 2.16.1, GNU C Compiler 3.4.4, GNU Debugger 6.8 (with RSP support), Linux Kernel 2.6.23, uClibc 0.9.28.3 and Or1ksim 0.3.0rc2.



  • EAN 3. Howto: Porting the GNU Debugger: Practical Experience with the OpenRISC 1000 Architecture (Issue 2, November 2008).

    This application note is aimed at engineers porting GDB to a new architecture for the first time.

    The GNU Debugger software distribution includes a guide for users and a 100-page guide to its internals. The latter is a document primarily aimed at those wishing to become developers of new functionality in GDB, rather than engineers wishing to port the existing functionality to a new architecture. Whilst an admirable document, it is not the place to find the "big picture" about how GDB works, is far from complete and in many places out of date.

    This application note fills the gap between the user guide and the GDB internals document for engineers porting GDB to a new architecture. It is based on the author's experience porting GDB 6.8 to the OpenRISC 1000 architecture, and includes practical examples from that work.



  • EAN 4. Howto: GDB Remote Serial Protocol: Writing a RSP Server (Issue 2, November 2008).

    This application note is aimed at engineers writing a GDB Remote Serial Protocol Server for the first time.

    The GNU Debugger software distribution includes a User Guide which documents the GDB Remote Serial Protocol for communicating with remote targets. The distribution also includes "stub" code for use by those implementing their own RSP server.

    This application note provides practical advice to supplement the GDB User Guide for engineers writing a GDB RSP server. It is based on the author's experience implementing the first RSP server to support GDB 6.8 on the OpenRISC 1000 architecture, and includes practical examples from that work.



  • EAN 5. Using JTAG with SystemC: Implementation of a Cycle Accurate Interface (Issue 1, January 2009).

    This application note is aimed at engineers needing to interface SystemC to cycle accurate models of devices implementing the IEEE 1149.1 JTAG interface.

    Cycle accurate models of devices in SystemC may be written by hand. More commonly they are generated automatically by tools such as Verilator, ARC VTOC and Carbon Design Systems ModelStudio. They may also be implemented using SystemC interfaces to traditional event driven simulation.

    Directly interfacing to the JTAG cycle accurate ports of a SystemC model is a complex task, requiring careful modeling of the JTAG Test Access Port (TAP) state machine.

    This application note specifies a more abstract interface, allowing the user to simply read and write hardware registers through JTAG. The interface takes responsibility for ensuring the correct sequence of signals is sent through the TAP to achieve the desired action.

    The application note and its associated reference implementation provide a practical tool for engineers involved in the detailed design, verification and modeling of complex FPGAs and ASICs.



  • EAN 6. High Performance SoC Modeling with Verilator: A Tutorial for Cycle Accurate SystemC Model Creation and Optimization (Issue 1, February 2009).

    This application note is a tutorial in building high performance SystemC cycle accurate models from Verilog RTL.

    Typical uses are:

    • Detailed performance analysis of systems, based on the actual hardware implementation running with its embedded software.
    • Implementation of low level firmware, such as board support packages, codecs and specialist device drivers, which rely on exact behavior of SoC peripherals.
    • Software optimization of components such as device drivers and codecs, where optimal performance depends on precise integration with the hardware architecture.

    Embecosm are also able to present the content of this tutorial as a two day seminar. Please contact us for more details.



  • EAN 7. Integrating the GNU Debugger with Cycle Accurate Models: A Case Study using a Verilator SystemC Model of the OpenRISC 1000 (Issue 1, March 2009).

    This application note demonstrates how to integrate the GNU Debugger with SystemC cycle accurate models. It builds on the techniques described in EAN 5, Using JTAG with SystemC and EAN 6, High Performance SoC Modeling with Verilator.

    The result is a GDB Server that makes firmware development and debugging on the cycle accurate model highly productive. Typical uses are:

    • Implementation of low level firmware, such as board support packages codecs and specialist device drivers, which rely on exact behavior of SoC peripherals.
    • Software optimization of components such as device drivers and codecs, where optimal performance depends on precise integration with the hardware architecture.
    • Detailed performance analysis of systems, based on the actual hardware implementation running with its embedded software.

    The tutorial demonstrates the techniques using the OpenRISC Reference Platform System-on-Chip (ORPSoC), a 32-bit SoC. Full GDB debugging functionality is provided with a cycle accurate model running at nearly 100kHz.

    Embecosm are also able to present the content of this tutorial as a three day seminar. Please contact us for more details.



  • EAN 8. Howto: Using DejaGnu for Testing: A Simple Introduction (Issue 1, April 2010).

    DejaGnu is the testing framework for the GNU project. It is a powerful system for setting up automated test environments that are highly portable. However the documentation of this technology can prove daunting for the first time user.

    This application note was written in response to the author's frustration when setting up a DejaGnu test framework without any prior experience. It provides a simple guide for any engineer setting up such an environment for the first time.

    Robust testing is central to all Embecosm's work. We are able to present the content of this tutorial as a one day seminar. We can also offer consultancy to help users set up their own test environments. Please contact us for more details.



  • EAN 9. Howto: Porting Newlib: A Simple Guide (Issue 1, July 2010).

    Newlib is a C library intended for use on embedded systems. It is a collection of several library parts, all under free software licenses that make them easily usable on embedded products. It is also commonly used when testing GNU tool chains.

    Embecosm has worked with a number of customers to port Newlib to embedded targets. This application note shares some of our expertise for those who wish to explore Newlib for themselves. The examples are all based on the version of Newlib 1.18.0 for the OpenRISC 1000 architecture.

    Library implementation is one aspect of Embecosm's consultancy in open source software development. We reply on robust libraries for reliable tool validation. Please contact us, to learn more about our services in this area.



  • EAN 10. Howto: Implementing LLVM Integrated Assembler: A Simple Guide (Issue 1, October 2012).

    The LLVM integrated assembler is an alternative to using a standalone assembler with the LLVM compiler. It uses the data from TableGen to translate from symbolic assembler to binary instructions, which are emitted as an ELF file.

    This is the first in a series of application notes on LLVM development written by Simon Cook of Embecosm. It shares some of our expertise for those who wish to develop their own LLVM assembler The examples are all based on the implementation of the LLVM assembler for the OpenRISC 1000 architecture.

    LLVM development is one aspect of Embecosm's consultancy in open source software development. We provide production quality open source compiler development, essential to any high quality software development tool chain. Please contact us, to learn more about our services in this area.



  • EAN 11. Howto: CVS to Git: Efficient Multi-Module Migration (Issue 1, February 2013).

    This application note describes the process of migrating CVS modules to Git repositories, and is aimed at developers or administrators who wish to migrate repositories on either a one time or continual basis.

    Using the Sourceware repository for GNU tool chain components as an example throughout, the application note draws on the author's experience in building a script for the conversion of many CVS modules from this repository.



  • EAN 12. Chiphack for teens: Silicon chip design for teenagers (Issue 1, October 2014)

    Chiphack is a workshop which teaches the basics of silicon chip design. In this application note it has been redesigned to allow teenagers to learn silicon chip design. No previous knowledge of FPGAs or even programming/computing is needed. The goal of this guide is for teens to come away with enough know-how to be interested and able to learn more about both FPGAs and computer science. An FPGA development board is required and a Terasic DE0 Nano is recommended. Other boards may be used, but may require different tools.

  • EAN13. An Altruistic Processor (AAP): A reference Harvard architecture for embedded compiler development (Issue 2.1, December 2015)

    This application note describes a reference Harvard architecture for embedded compiler development. AAP is an architecture specification designed for experimenting with various features in compiler back ends. In particular it has features that are common within small deeply embedded systems. It is also designed to be easy to use in demonstrations and education/training. This includes hardware and simulator implementation as well as the tool chain and library implementation. The design is based on no processor in particular, although as an open hardware design, it is inspired by the OpenRISC and RISC-V projects. There are features drawn from a wide range of processors developed over the past 30 years. Indeed the branch-and-link operation goes back even further, to the IBM 360.

  • EAN 14. An Altruistic Processor (AAP): A Student Implementation for FPGA (Issue 1, November 2015)

    It was a bright cold day in August, and the clocks were striking 50 million times a second. Dan's implementation of an AAP processor is complete, and he's ready to share it with the world.

    I am a student, with no previous knowledge of making a processor. Therefore this is my first attempt, and is by no means a definitive guide to creating a processor. Its purpose is to allow a novice to grasp the basics via an easy to understand processor.

    We will take our design from Embecosm's previous application note, AAP: An Altruistic Processor. Our hardware description language of choice will be Verilog, which if you have not come across will look a lot like C. For this Application Note you will not need to already know Verilog, but it would be advisable to have a quick read and play with my last application note, ChipHack For Teens.