Surveying the Free and Open Source RISC-V Ecosystem

The RISC-V workshop in Barcelona starts at lunchtime today, 7 May.  I’ll be there with my colleagues Graham Markall, Mary Bennett and Ian Loveless.  We’ll be talking about upstreaming GDB for RISC-V and building CGEN based assemblers and simulators.  To mark the occasion, I thought it would be useful to provide a short survey of the free and open source RISC-V ecosystem.

In the 8 years since it was introduced the RISC-V open instruction set architecture has been widely taken up by industry and academia worldwide.  Many of the implementations, particularly within companies are proprietary, but there are many free and open source implementations available, some whose quality has been proven through multiple successful ASIC tape outs.  And whether proprietary or free, all these implementations rely on free software tools.  This post looks at those free implementations and associated software tool chain.

Free Hardware implementations

We can  divide the available implementations into three groups.  First are those which are production ready, either proven as ASIC’s or on FPGA.

  • Ariane. A 64-bit core with multiple privilege levels from the PULP project at ETH Zurich and the University of Bologna.  Implements RV64IMC, written in SystemVerilog and released under the SolderPad Hardware License. Source code at github.com/pulp-platform/ariane.
  • f32c. A simple 32-bit core developed for the FPGArduino project. Implements RV32I, written in VHDL and released under a BSD license. Source code at github.com/f32c/f32c
  • lowRISC. Developed by Rob Mullins, Alex Bradbury and others in Cambridge, UK.  Reuses the Rocket and RI5CY cores to implement RV64G and RV32IMC, written in Chisel (Rocket) and SystemVerilog (RI5CY) and released under BSD and Apache licenses. Source code at github.com/lowRISC/lowrisc-chip.
  • Orca. Developed by VectorBlox Inc as an alternative host to VectorBlox’s Proprietary Matrix processor, MXP.  Implements RV32I/RV32IM, written in VHDL and released under a MIT style license. Source code at github.com/VectorBlox/orca.
  • PicoRV32. A very small fast core for FPGA by Clifford Wolf.  Implements RV32I, RV32E, RV32IC, RV32IM and RV32IMC, written in SytemVerilog and released under the ISC license.  Source code at github.com/cliffordwolf/picorv32.
  • RI5CY. The main 32-bit core from the PULP project at ETH Zurich and the University of Bologna.  Implements RV32IMC and RC32IMFC, written in SystemVerilog and released under the SolderPad Hardware License.  Source code at github.com/pulp-platform/riscv.
  • River. A reimplementation of Rocket in VHDL by GNSS Sensor Limited in Moscow, Russia.  Implements RV64G, written in VHDL and released under a BSD license.  Source code at github.com/sergeykhbr/riscv_vhdl.
  • Rocket. The original demonstrator of RISC-V developed by Krste Asanović, David A Patterson and their team at the University of California, Berkeley, USA.  Implements RV64G, written in Chisel and released under a BSD license.  Source code at github.com/freechipsproject/rocket-chip.
  • Zero-riscy & Micro-riscy. Area optimized 32-bit cores from the PULP project at ETH Zurich and the University of Bologna.  Implement RV32IMC (Zero-riscy), RV32EC (Micro-riscy), written in SystemVerilog and released under the SolderPad Hardware License.  Source code at github.com/pulp-platform/zero-riscy.

Then we have educational designs.  There is no implication of lower quality than production designs, but these projects are primarily educational, and that is reflected in design approaches and project structure.

  • Clarvi.  Developed by Simon Moore and Rob Mullins at Cambridge University for teaching.  Implements RV32I, written in SystemVerilog and licensed under the MIT license.  Source code at github.com/ucam-comparch/clarvi.
  • Sodor.  A collection of RISC-V implementations in Chisel developed for educational purposes by Christopher Celio at UC Berkeley.  All implement RV32I, are written in SystemVerilog and licensed under the BSD 3-clause license.  Source code at github.com/ucb-bar/riscv-sodor.

Finally there are a group of projects, which can be regarded as “works in progress”.  By making their design available before they are complete, these projects allow others to engage early and contribute to the work.

  • mriscv. A microcontroller SoC developed by Ckristian Duran inspired by the Rocket chip.  Written in Verilog and released under the MIT license.  Source code is at github.com/onchipuis/mriscvcore.
  • μRV. A small footprint 32-bit RISC-V core intended for embedded real-time applications using FPGAs developed at CERN.  Written in Verilog and released under LGPLv3.  Source code at github.com/twlostow/urv-core.
  • Shakti. A program at IIT Madras to develop a family of RISC-V processor cores from the E-class core (RV32I) for small embedded applications to the S-class core (RV64G) for high performance computing (HPC) applications.  Currently  only two smaller cores have implementations.  Written in Bluespec and released under a BSD 3-clause license.  Source code at bitbucket.org/casl/shakti_public.
  • Tom Thumb. A very small RV32I implementation in VHDL and running on a Terasic DE0-nano and other Altera Cyclone IV boards.  Written in VHDL and released under the MIT license.  Source code is at github.com/maikmerten/riscv-tomthumb.
  • Z-scale. A tiny 32-bit RISC-V core generator for microcontrollers and embedded systemsdeveloped by Yunsup Lee, Albert Ou and Albert Magyar at UC Berkeley in 2015.  Now deprecated and incorporated into Sodor (see above) as the 3-stage pipeline.  Implements RV32IM, written in Verilog and licensed under a BSD license.  Source code at  github.com/ucb-bar/vscale.

Software Tools

Both GNU and LLVM based tool chains are available, although at present the GNU tool chain is more mature.  The components of the GNU tool chain are as follows.

The components of the LLVM tool chain are as follows.

More information

Embecosm is currently working on an application note providing ore detail on the free RISC-V ecosystem, which will also survey the options available for free modeling and pre-silicon debug and testing of RISC-V.  This will be published later in 2018.