Category: RISC_V

Up-To-Date RISC-V GCC Tool Chain Packages

The global hardware and software community is developing a huge range of RISC-V based solutions.  As part of its commitment to that community, Embecosm is making freely available pre-built up-to-date GCC tool chains.  This will ensure that software is built with the latest RISC-V compiler features and optimizations. Read More

GCC support for the draft Bit Manipulation Extension for RISC-V

Introduction One of the currently proposed draft ISA extensions for RISC-V is the Bit Manipulation Instructions extension (from henceonwards referred to as the “Bitmanip” or “BMI” extension.) It proposes to provide fast and direct instructions for commonly-used bitwise operations, often… Read More

A dive into RI5CY core internals

What is RI5CY? RI5CY is a 4-stage in-order pipelined RISC-V core written in SystemVerilog. It has become very popular for many applications, including being adopted as the first Core-V core in the OpenHW Group family, as… Read More

Buildroot Support for 32-bit RISC-V

The patches that I submitted to add 32-bit RISC-V architecture support to Buildroot have recently been committed upstream. As part of this patchset a configuration was added to enable the Buildroot autobuilders so that any potential build… Read More

Buildroot menuconfig screen

Adding RISC-V 64-bit Support to Buildroot

Background I have been working on adding RISC-V 64-bit architecture support to Buildroot. Buildroot is an embedded Linux build system that generates complete system images from source for a wide range of boards and processors. Buildroot uses makefiles… Read More

Protecting secret data with Stack Erase

Hi, I’m Sam Leonard, and I’m going into my second year of A-levels. I’m at Embecosm for a week as a work experience student, working on producing an exploit as a proof of concept for the Stack Erase feature that… Read More

Surveying the Free and Open Source RISC-V Ecosystem

The RISC-V workshop in Barcelona starts at lunchtime today, 7 May.  I'll be there with my colleagues Graham Markall, Mary Bennett and Ian Loveless.  We'll be talking particularly about upstreaming GDB for RISC-V and building CGEN based assemblers and simulators.  To mark the occasion, I thought it would be useful to provide a short survey of the free and open source RISC-V ecosystem. Read More