GSoC Projects: Accelerating RISC-V for AI/ML Applications

Embecosm has been working with Southampton University as an industrial partner for it’s MEng final year Group Design Projects. The scope of this project was to create a RISC-V based instruction set extension to accelerate AI and machine learning applications. Read More

GCC Rust – How it can be achieved

In conjunction with the recent announcement of the GNU tool chain implementation of Rust supported by Open Source Security, Inc. and Embecosm we want to outline how the project will move forward. To create a trustworthy compiler… Read More

Comparing Compilers: A Statistical Perspective

Here, we discuss an interesting problem: the task of analyzing the respective performance of two compilers to see which one is better. Explicitly, we have two (or more) different compilers that we wish to compare, and we’re trying to quantify… Read More

Up-To-Date RISC-V GCC Tool Chain Packages

The global hardware and software community is developing a huge range of RISC-V based solutions.  As part of its commitment to that community, Embecosm is making freely available pre-built up-to-date GCC tool chains.  This will ensure that software is built with the latest RISC-V compiler features and optimizations. Read More

Face Detection with the EdgeTPU using Haar Cascades

Introduction I have been exploring the capabilities of the Google Coral development board and working towards a functional face recognition implementation on the embedded device. In a previous blogpost, I discussed an overall view of how the… Read More

GCC support for the draft Bit Manipulation Extension for RISC-V

Introduction One of the currently proposed draft ISA extensions for RISC-V is the Bit Manipulation Instructions extension (from henceonwards referred to as the “Bitmanip” or “BMI” extension.) It proposes to provide fast and direct instructions for commonly-used bitwise operations, often… Read More

A dive into RI5CY core internals

What is RI5CY? RI5CY is a 4-stage in-order pipelined RISC-V core written in SystemVerilog. It has become very popular for many applications, including being adopted as the first Core-V core in the OpenHW Group family, as… Read More